Assignment #4

SPARC INSTRUCTION SET

BY

ASHISH GUPTA ( 98131)

ANGSHUMAN PARASHAR (98123)

Complete Instruction Set of SPARC V8 will be implemented in the project ( SparcSimulator ).

The condition code register on the SPARC has four bits: Z (Zero), N (Negative), C (Carry), and V (oVerflow). The standard arithmetic operations (e.g., addition and subtraction) do not update the bits in the condition code register. Instead, there are special operations that update the condition code register. The names for these operations have a suffix of ``cc'' to indicate that they update the bits in the condition code register.

In most cases, the effect that an operation has on the condition codes is just what you would expect. Most of these operations set the Z bit when the result of the operation is zero, and clear this bit when the result is nonzero. Similarly, most of these operations set the N bit when the result of the operation is negative, and clear this bit when the result is nonnegative. The V bit is usually set when the (signed integer) result of the operation cannot be stored in 32 bits, and cleared when the result can be stored in 32 bits. Finally, the C bit is set when the operation generates a carry out of the most significant bit, and cleared otherwise.

In most contexts, you will be most interested in the N and Z bits of the condition code register and we will emphasize these bits in the remainder of this lab.

INSTRUCTIONS

1. Data Movement Instructions

Instruction |
Description |
Example |

ldsb address, rd |
Load signed byte from addr |
ldsb [%r1], %r2 |

ld address, rd |
Load signed word from addr |
ld [%r1], %r2 |

ldub address, rd |
Load unsigned byte from addr |
ldub [%r1], %r2 |

stb rs, address |
Stores byte to addr |
stb %r1, [%r2] |

sth rs, address |
Stores halfword to addr |
sth %r1, [%r2] |

st rs, address |
Stores word to addr |
st %r1, [%r2] |

sethi const22, rd |
Sets upper 22 bits of rd with const |
sethi 123,%r1 |

2. Arithmetic Instructions

Instruction |
Description |
Example |

add/addcc rs1, rs2/const, rd |
reg[rd] = reg[rs1] + reg[rs2] |
add %r1, %r2, %r3 |

sub/subcc rs1, rs2/const, rd |
reg[rd] = reg[rs1] - reg[rs2] |
sub %r1, %r2, %r3 |

addx/addxcc rs1, rs2/const, rd |
reg[rd] = reg[rs1] + reg[rs2] (with carry) |
addx %r1, %r2, %r3 |

subx/subxcc rs1, rs2/const, rd |
reg[rd] = reg[rs1] - reg[rs2] (with borrow) |
subx %r1, %r2, %r3 |

cmp %r1,%r2 |
Sets appropriate condition codes |
cmp %r1,%r2 |

3.Logical and Shift Instructions

Instruction |
Description |
Example |

and rs1,rs2/const,rd |
reg[rd]=reg[rs1] AND reg[rs2] |
and %r1,%r2,%r3 |

or rs1,rs2/const,rd |
reg[rd]=reg[rs1] OR reg[rs2] |
or %r1,%r2,%r3 |

orn rs1,rs2/const,rd |
reg[rd]=reg[rs1] NOR reg[rs2] |
orn %r1,%r2,%r3 |

4. Branch and Control Transfer Instructions

Instruction |
Description |
Example |

ba target |
branch always |
ba loop1 |

bne target |
branch not equal |
bne loop1 |

be target |
branch equal |
be loop1 |

bg target |
branch greater |
bg loop1 |

ble target |
branch less than or equal |
ble loop1 |

bge target |
branch greater than or equal |
bge loop1 |

bl target |
branch less than |
bl loop1 |

bgu target |
branch greater (unsigned ) |
bgu loop1 |

bleu target |
branch less or equal ( unsigned ) |
bleu loop1 |

**Note** : Like most RISC machines, the SPARC uses a branch delay slot. By default, the instruction following a branch instruction is executed whenever the branch instruction is executed.

5. Procedure Instructions

Instruction |
Description |
Example |

call target |
Jump to call-address and save PC into %r15 |
call proc |

jmpl rs , rd |
Jumps to [rs] and saves PC to rd |
jmpl %r1,%r2 |

save rs1,rs2,rd save rs1,const,rd |
Provide new register window . rd = rs1 + rs2 (For stack pointer updation ) |
save %sp,-16,%sp |

restore rs1,rs2,rd restore rs1,const,rd |
Restore old register window. rd = rs1 + rs2 ( For stack pointer updation ) |
restore %sp,16,%sp |