Datapath for SPARC Processor
by Ashish Gupta (98131)
Angshuman Parashar ( 98123)
An Architecture for the SPARC
We begin by describing the datapath and its associated control sig-nals.
There are 15 instructions that are grouped into four for-mats
according to the leftmost two bits of the coded instruction. The Processor
Status Register %psr is also shown.
A datapath for the SPARC is illustrated in the accompanying hand drawn diagram. The datapath contains 32 user-visible data registers (%r0 %r31), the program counter (%pc), the instruction register (%ir), the ALU, four temporary registers not visible at the user level (%temp0 %temp3), and the connections among these components.
The number adjacent to a diagonal slash on some of the lines is a simplification that indicates the number of separate wires that are represented by the corresponding single line. Registers %r0 %r31 are directly accessible by a user. Register %r0 always contains the value 0, and cannot be changed. The %pc register is the program counter, which keeps track of the next instruction to be read from the main memory. The user has direct access to %pc only through the call and jmpl instructions. The temporary registers are used in interpreting the ARC instruction set, and are not visible to the user. The %ir register holds the current instruction that is being executed. It is not visible to the user.
The datapath consists of five stages namely :
The existence of a branch delay allows branches to progress normally through the pipeline if they can determine the branch target early enough to fetch the second instruction entering the pipeline after a branch. The branch target instruction is speculatively fetched before the condition codes have been updated. If it turns out that the condition is met , then execution of the target instruction can continue without interruption ; otherwise the next instruction in sequence is fetched .
Instruction Format Description
Instruction format for SPARC and machine coding for SPARC instructions.
The ALU performs one of 16 operations on the A and B busses according to the
ALU opcode sent to it by the control depending on the instruction opcode. For every ALU operation, the 32-bit result is placed in the pipeline register following it.
The ANDCC and AND operations perform a bit-by-bit logical AND of corre-sponding bits on the A and B busses. Note that only operations that end with"CC" affect the condition codes, and so ANDCC affects the condition codes
whereas AND does not. (There are times when we wish to execute arithmetic and
logic instructions without disturbing the condition codes.) The ORCC and OR
operations perform a bit-by-bit logical OR of corresponding bits on the A and B
busses. The NORCC and NOR operations perform a bit-by-bit logical NOR of
corresponding bits on the A and B busses. The ADDCC and ADD operations
carry out addition using twos complement arithmetic on the A and B busses.